1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to a semiconductor memory device outputting a test mode signature in a test mode.
2. Description of the Prior Art
FIG. 15 is a block diagram showing the structure of a conventional dynamic random access memory (hereinafter referred to as "DRAM"). Referring to FIG. 15, this DRAM comprises a clock generation circuit 101, a row and column address buffer 102, a row decoder 103, a column decoder 104, a memory mat 105, an input buffer 108 and an output buffer 109, and the memory mat 105 includes a memory array 106 and a sense amplifier+ input/output control circuit 107.
The clock generation circuit 101 selects a prescribed operation mode on the basis of externally supplied control signals ext.ZRAS, ext.ZCAS and ext.ZWE and controls the overall DRAM.
The row and column address buffer 102 generates row address signals RA0 to RAm and column address signals CA0 to CAm on the basis of externally supplied address signals ext.A0 to ext.Am (m:integer of at least 0) and supplies the generated row address signals RA0 to RAm and column address signals CA0 to CAm to the row decoder 103 and the column decoder 104 respectively.
The memory array 106 includes a plurality of memory cells each storing 1-bit data. The plurality of memory cells are previously divided into groups each including n (n: integer of at least 1) memory cells. Each memory cell group is arranged on a prescribed address decided by a row address and a column address.
The row decoder 103 specifies a row address of the memory array 106 in response to the row address signals RA0 to RAm supplied from the row and column address buffer 102. The column decoder 104 specifies a column address of the memory array 106 in response to the column address signals CA0 to CAm supplied from the row and column address buffer 102.
The sense amplifier+input/output control circuit 107 connects the n memory cells of the address specified by the row decoder 103 and the column decoder 104 to an end of a data bus DB. Another end of the data bus DB is connected to the input buffer 108 and the output buffer 109. The input buffer 108 supplies externally input data D1 to Dn to the selected n memory cells through the data bus DB in response to the control signal ext.ZWE in a write mode. The output buffer 109 outputs read data D1 to Dn from the selected n memory cells in response to an externally input control signal ZOE in a read mode.
In the read mode, the external address signals ext.A0 to ext.Am are supplied while the external control signal ext.ZRAS is set low for activation and thereafter the external control signal ext.ZCAS is set low for activation. Thus, the row decoder 103 and the column decoder 104 select n memory cells so that read data from the n memory cells are output through the sense amplifier+input/output control circuit 107 and the output buffer 109.
In the write mode, the external data D1 to Dn and the external address signals ext.A0 to ext.Am are supplied while the external control signal ext.ZRAS is set low for activation and thereafter the external control signals ext.ZCAS and ext.ZWE are set low for activation. Thus, the row decoder 103 and the column decoder 104 select n memory cells so that the data D1 to Dn are written in the selected n memory cells through the input buffer 108 and the sense amplifier+input/output control circuit 107.
Such a DRAM stores a test circuit for testing whether or not the DRAM is normal before shipping, and various test modes can be set through input timing for the external control signals ext.ZRAS, ext.ZCAS and ext.ZWE and combination of the external address signals ext.A0 to ext.Am.
No problem arises if the DRAM is regularly set in a desired test mode in testing. If the DRAM is set in a test mode different from the desired one or not set in a test mode, however, no desired test is made but a defective unit may be shipped.
When setting a test mode of forcibly supplying an internal power supply voltage of the DRAM from outside, for example, the internal power supply voltage cannot be externally monitored and it is impossible to determine whether or not the internal power supply voltage is at the externally supplied level. Therefore, a desired test may not be performed but a defective unit may be shipped.
If the DRAM outputs a test mode signature responsive to the test mode only when set in the test mode, however, it is possible to determine whether or not the test mode is set by monitoring the test mode signature. Therefore, the DRAM stores a circuit for generating a test mode signature responsive to a test mode and outputting the same. A part of the DRAM related to test mode signatures is now described in detail.
FIG. 16 is a block diagram showing the structure of a part of the conventional DRAM related to test mode setting. Referring to FIG. 16, this DRAM includes input circuits 111 to 113, a WCBR determination circuit 114, a super VIH determination circuit 115 and an address determination circuit 116.
The input circuits 111 to 113 transmit the external control signals ext.ZRAS, ext.ZCAS and ext.ZWE and the external address signals ext.A1 to ext.A3 to the DRAM. The WCBR determination circuit 114 sets an internal control signal WCBR high for activation when the external control signals ext.ZCAS and ext.ZWE fall low in advance of the external control signal ext.ZRAS.
The super VIH determination circuit 115 is activated responsively when the signal WCBR goes high for activation, and sets a signal .phi.SVIH high for activation responsively when a super VIH level SVIH sufficiently higher than a power supply voltage VCC is supplied to an input terminal for the external address signal ext.A1.
The address determination circuit 116 is activated responsively when the signal .phi.SVIH goes high for activation for setting any of test signals TM1 to TM4 high for activation in response to the combination (00 to 11) of the levels of the external address signals ext.A2 and ext.A3, and reset by a reset signal RES.
As shown in FIG. 17, the address determination circuit 116 includes inverters 121 to 125, AND gates 126 and 127, clocked inverters 128 and 129 and NOR gates 130 and 131. The external address signal ext.A2 is input in first input nodes of the AND gates 126 and 127 through an input circuit 113a. The external address signal ext.A3 is input in a second input node of the AND gate 126 through an input circuit 113b and input in a second input node of the AND gate 127 through the input circuit 113b and the inverter 121.
Output signals .phi.126 and .phi.127 from the AND gates 126 and 127 are input in first input nodes of the NOR gates 130 and 131 through the clocked inverters 128 and 129 respectively. The signal .phi.SVIH is input in the gates of N-channel MOS transistors of the clocked inverters 128 and 129, and input in the gates of P-channel MOS transistors of the clocked inverters 128 and 129 through the inverters 122 and 123. The reset signal RES is input in second input nodes of the NOR gates 130 and 131. The inverters 124 and 125 are connected between output nodes and the first input nodes of the NOR gates 130 and 131 respectively. The NOR gates 130 and 131 output the signals TM1 and TM2.
When the signals ext.A2 and ext.A3 are both high, i.e., when the combination is "11", the output signals .phi.126 and .phi.127 of the AND gates 126 and 127 go high and low respectively. When the signals ext.A2 and ext.A3 are high and low respectively, i.e., when the combination is "10", the output signals .phi.126 and .phi.127 of the AND gates 126 and 127 go low and high respectively. When the signal .phi.SVIH goes high for activation, the clocked inverters 128 and 129 are activated so that the signals .phi.126 and .phi.127 are input in the first input nodes of the NOR gates 130 and 131 through the clocked inverters 128 and 129.
The signal .phi.126 is latched by a latch circuit formed by the NOR gate 130 and the inverter 124 to form the signal TM1. The signal .phi.127 is latched by a latch circuit formed by the NOR gate 131 and the inverter 125 to form the signal TM2. The clocked inverters 128 and 129 are inactivated when the signal .phi.SVIH goes low, and the signals TM1 and TM2 are reset low when the reset signal RES goes high.
The signal TM3 goes high when the external address signals ext.A2 and ext.A3 go low and high respectively and the signal .phi.SVIH goes high. The signal TM4 goes high when the external address signals ext.A2 and ext.A3 both go low and the signal .phi.SVIH goes high. When any of the test signals TM1 to TM4 goes high, the DRAM is set in a test mode responsive to this signal.
FIG. 18 is a block diagram showing the structure of a part of this DRAM related to generation and output of test mode signatures. Referring to FIG. 18, the DRAM includes a test mode signature generation circuit 132 and an output buffer 133. It is assumed that the bit number n of data which can be simultaneously input/output is 4.
The test mode signature generation circuit 312 is activated responsively when the signal WCBR goes high for activation and outputs the test signals TM1 to TM4 as test mode signatures TMSIG1 to TMSIG4. As shown in FIG. 19, the test mode signature generation circuit 132 includes NAND gates 141 to 144 and inverters 145 and 148. The signal WCBR is input in first input nodes of the NAND gates 141 to 144. The signals TM1 to TM4 are input in second input nodes of the NAND gates 141 to 144 respectively. Output signals from the NAND gates 141 to 144 are inverted by the inverters 145 to 148 respectively, to form the test mode signatures TMSIG1 to TMSIG4.
When the signal WCBR is low for inactivation, all test mode signatures TMSIG1 to TMSIG4 are fixed low. When the signal WCBR is high for activation, the test signals TM1 to TM4 pass through the NAND gates 141 and 144 and the inverters 145 to 148 to form the test mode signatures TMSIG1 to TMSIG4.
The output buffer 133 outputs data signals D1 to D4 in accordance with internal data signals ZRDH1 to ZRDH4 and ZRDL1 to ZRDL4 in a general read mode, and outputs test mode signatures TMSIG1' to TMSIG4' in accordance with the test mode signatures TMSIG1 to TISIG4 in the test mode.
As shown in FIG. 20, the output buffer 133 includes an output buffer 133a provided in correspondence to the signals ZRDH1, ZRDL1 and TMSIG1. In addition to the buffer 133a, the output buffer 133 includes three buffers provided in correspondence to the signals ZRDH2, ZRDL2 and TMSIG2, . . . , ZRDH4, ZRDL4 and TMSIG4 respectively. The four buffers are identical in structure to each other, and hence only the buffer 133a is described.
The buffer 133a includes inverters 151 to 156, a level shifter 157 and N-channel MOS transistors 158 to 160. The N-channel MOS transistors 158 and 159 are connected in parallel between a line of the power supply potential VCC and a data input/output terminal 150 for the data signal D1. The N-channel MOS transistor 160 is connected between the data input/output terminal 150 and a line of a ground potential GND. The signal ZRDH1 is input in the gate of the N-channel MOS transistor 158 through the inverters 151 to 153 and the level shifter 157. The test mode signature TMSIG1 is input in the gate of the N-channel MOS transistor 159. The signal ZRDL1 is input in the gate of the N-channel MOS transistor 160 through the inverters 154 to 156. An output signal .phi.157 of the level shifter 157 goes low when an input signal .phi.133 is low, and reaches a step-up potential VPP when the input signal .phi.133 is high.
When the signal ZRDH1 goes low for activation, the level shifter 157, i.e., the output signal .phi.157 reaches the step-up potential VPP, the N-channel MOS transistor 158 is rendered conductive, and the data signal D1 goes high. When the test mode signature TMSIG1 goes high for activation, the N-channel MOS transistor 159 is rendered conductive and the test mode signature TMSIG1' goes high. When the signal ZRDL1 goes low for activation, the N-channel MOS transistor 160 is rendered conductive and the data signal D1 goes low.
FIG. 21 is a timing chart showing operations of the part of the DRAM shown in FIGS. 16 to 20 related to the test mode signatures. For simplifying the illustration, the following description is made with reference to only operations of a part related to the test mode signature TMSIG1.
The signals ext.ZRAS, ext.ZCAS and ext.ZWE fall low at timing of WCBR, the signal WCBR goes high for activation, and the super VIH determination circuit 115 and the test signature generation circuit 132 are activated. The super VIH level SVIH is supplied to the input terminal for the external address signal ext.A1, the signal .phi.SVIH goes high for activation, and the address determination circuit 116 is activated. The external address signals ext.A2 and ext.A3 are both set high, the signal TM1 goes high and the test mode signatures TMSIG1 and TMSIG1' also go high. It is possible to detect that the DRAM is set in a test mode responsive to the signal TM1 by detecting that the test mode signature TMSIG1' is high.
However, the conventional DRAM is provided with the dedicated N-channel MOS transistor 159 for outputting the test mode signatures TMSIG1' to TMSIG4' while the size of this N-channel MOS transistor 159 is increased for improving resistance against a surge voltage supplied to the data input/output terminal 150, and hence the layout area of the output buffer 133 is disadvantageously increased.
The level shifter 157 for the test mode signature TMSIG1 is omitted in order to reduce the layout area of the output buffer 133, and hence the high level of the test mode signature TMSIG1' is VCC-Vth, where Vth represents the threshold voltage of the N-channel MOS transistor 159, lower than the power supply potential VCC.
In addition, the conventional DRAM regularly outputs the test mode signatures TMSIG1' to TMSIG4' when set in the test mode, and hence the test mode signatures TMSIG1' to TMSIG4' may collide with read data.